Multi-mode power amplifier

ABSTRACT

There is provided a multi-mode power amplifier operable in a low power mode having a preset power range and in a high power mode having a power range higher than the power range of the low power mode. The multi-mode power amplifier includes: a high power amplifying unit including at least one cascode amplifier to amplify an input signal to a high power level having a preset power range; a low power amplifying unit sharing a common source node of the at least one cascode amplifier to amplify the input signal to a low power level having a power range lower than the high power level; and a coupling unit coupling a transfer path of a signal output from the high power amplifying unit and a transfer path of a signal output from the low power amplifying unit to each other.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority of Korean Patent Application No.10-2011-0049888 filed on May 26, 2011, in the Korean IntellectualProperty Office, the disclosure of which is incorporated herein byreference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a multi-mode power amplifier operablein a low power mode having a preset power range, and, in a high powermode having a power range higher than that of the low power mode.

2. Description of the Related Art

Recently, blocks configuring a wireless transceiver have beenimplemented using a complementary metal oxide semiconductor (CMOS)process technology and have been integrated in a single chip. However,among these blocks of the wireless transceiver, only a power amplifierhas been implemented using an indium gallium phosphide (InGaP)/galliumarsenide (GaAs) heterojunction bipolar transistor (HBT) process.However, the above-mentioned InGAP/GaAs HBT process incurs manufacturingcosts higher than those of the CMOS process, needs to be implemented ina multi-chip structure, and there may be difficulty in coupling a blockformed thereby with an adjusting circuit block implemented by the CMOSprocess in order to improve linearity. Due to the above-mentionedreasons, research into a CMOS based power amplifier has been activelyundertaken.

Meanwhile, among configuring a wireless communications terminal,components associated with power amplification consume the greatestamount of power. Therefore, power amplifier power efficiency needs to beincreased in order to improve the entire call time. Since the wirelesscommunications terminal has an output power controlled according to adistance to a repeater, with reference to a probability density functionaccording to an output power of the wireless communications terminal, anefficiency improvement in a low output power backed off from the maximumpower output by 10 dB or more has a direct influence on an improvementin call time. That is, there is a need to increase power efficiency notonly in a high power mode having the maximum power output level, butalso in a low power mode having a power level lower than the maximumpower output level.

Therefore, the necessity for a multi-mode power amplifier performingdifferent power amplification operations in a low power mode and a highpower mode has been increased.

In the multi-mode power amplifier according to the related art, in thecase in which different signal transfer paths are formed for each of thepower modes, an impedance matching circuit is required for each of thesignal transfer paths, such that a circuit area increases andmanufacturing costs rise. Particularly, in the CMOS process, power lossis generated by a passive device for implementing the impedance matchingcircuit, such that power efficiency is reduced. In addition, even in acase in which an amplifier circuit is formed for each of the powermodes, input and output impedance matching circuits are required, suchthat a circuit area increases and manufacturing costs rise. In addition,power loss may be generated by a passive device, such that powerefficiency is reduced.

SUMMARY OF THE INVENTION

An aspect of the present invention provides a multi-mode power amplifierin which a common source node of a cascode amplifier is used in commonand an output is selectively connected to a secondary winding of acoupling unit, such that a separate impedance circuit is not required.

According to an aspect of the present invention, there is provided amulti-mode power amplifier including: a high power amplifying unitincluding at least one cascode amplifier to amplify an input signal to ahigh power level having a preset power range; a low power amplifyingunit sharing a common source node of the at least one cascode amplifierto amplify the input signal to a low power level having a power rangelower than the high power level; and a coupling unit coupling a transferpath of a signal output from the high power amplifying unit and atransfer path of a signal output from the low power amplifying unit toeach other.

The low power amplifying unit may include: an amplifying part includingan amplifier amplifying the input signal from the shared common sourcenode to the low power level; and a switching part including at least oneswitch opening or closing the transfer path of the signal through whichthe signal amplified from the amplifying part is transferred to thecoupling unit according to a selection of power modes.

The coupling unit may include a primary winding receiving the signalamplified from the high power amplifying unit and a secondary windingreceiving the signal amplified from the low power amplifying unit andelectromagnetically coupled to the primary winding to thereby couple thetransfer paths of the signals to each other.

The switching part may include a first switch connected between one endof the secondary winding and a ground to thereby transfer the signalamplified from the amplifying part to the secondary winding or connectone end of the secondary winding and the ground to each other.

The switching part further may include: a capacitor connected to theother end of the secondary winding from which the signal is output; anda second switch connected between the capacitor and the ground and beingswitched on or off together with the first switch, thereby connecting oropening between the capacitor and the ground.

The amplifying part may be an N type metal oxide semiconductor fieldeffect transistor (MOSFET) having a drain outputting the amplifiedsignal, a source connected to the common source node, and a gatereceiving a gate signal.

The high power amplifying unit may include: a driving amplifying partincluding first and second cascode amplifiers connected with each otherin parallel to thereby amplify the input signal according to a set gain;and a power amplifying part including third and fourth cascodeamplifiers connected with each other in parallel to thereby amplify thesignal amplified from the driving amplifying part according to a setgain.

The low power amplifying unit may share a common source node of thefirst or second cascode amplifier of the driving amplifying part.

The input signal may be a single signal or a balanced signal.

The high power amplifying unit may further include an impedance matchingpart matching an impedance of a transfer path of the signal betweendriving amplifying part and the power amplifying part.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, features and other advantages of thepresent invention will be more clearly understood from the followingdetailed description taken in conjunction with the accompanyingdrawings, in which:

FIG. 1 is a schematic view showing the configuration of a multi-modepower amplifier according to an embodiment of the present invention;

FIG. 2 is a simulation view of a resistance value viewed from a lowpower amplifying unit of a multi-mode power amplifier according to anembodiment of the present invention;

FIG. 3 is a graph showing linearity and efficiency of a multi-mode poweramplifier according to an embodiment of the present invention; and

FIG. 4 is a graph showing a power gain and efficiency of a multi-modepower amplifier according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Embodiments of the present invention will now be described in detailwith reference to the accompanying drawings.

FIG. 1 is a schematic view showing the configuration of a multi-modepower amplifier according to an embodiment of the present invention.

Referring to FIG. 1, a multi-mode power amplifier 100 according to anembodiment of the present invention may include a high power amplifyingunit 110, a low power amplifying unit 120, and a coupling unit 130. Inaddition, the above-mentioned multi-mode power amplifier 100 may beformed by a complementary metal oxide semiconductor (CMOS) process.

The high power amplifying unit 110 may be operated at the time of a highpower mode in which an input signal is amplified to a high power levelhaving a preset power level range, or the low power amplifying unit 120may be operated at the time of a low power mode in which an input signalis amplified to a low power level having a power level range lower thanthe high power level, according to a selection of a user. The couplingunit 130 may couple signal transfer paths from the high power amplifyingunit 110 and the low power amplifying unit 120 to each other.

More specifically, the high power amplifying unit 110 may include adriving amplifying part 111 primarily amplifying an input signal and apower amplifying part 112 reamplifying the amplified signal. Forexample, the driving amplifying part 111 may amplify a power level ofthe input signal to 15 dBm, and the power amplifying part 112 mayamplify a power level of the signal amplified by the driving amplifyingpart 111 to 30 dBm.

The driving amplifying part 111 may include at least one cascodeamplifier according to types of the input signal. That is, when theinput signal is a single signal, the driving amplifying part 111 mayinclude a single cascode amplifier, and when the input signal is abalanced signal, the driving amplifying part 111 may include two cascodeamplifiers. For reference, when the input signal is the balanced signal,a balun converting a single signal into a balanced signal may be used ina front end of the driving amplifying part 111. FIG. 1 shows a case inwhich the balanced signal is input by way of example; however, thepresent invention is not limited thereto. The driving amplifying part111 may include a first cascode amplifier 111 a and a second cascodeamplifier 111 b connected in parallel with the first cascode amplifier111 a.

The first cascode amplifier 111 a may include first and second metaloxide semiconductor field effect transistors (hereinafter, referred toas MOSFETs) N1 and N2 cascode-connected to each other. Likewise, thesecond cascode amplifier 111 b may include third and fourth MOSFETs N3and N4 cascode-connected to each other.

The first and second MOSFETs N1 and N2 may be common source connected toeach other, and the third and fourth MOSFETs N3 and N4 may be commonsource connected to each other. Gates of the second and fourth MOSFETsN2 and N4 may be connected to each other as a common gate and have agate signal Vg1 input thereto. A common source node of the first andsecond MOSFETs N1 and N2 and a common source node of the third andfourth MOSFETs N3 and N4 may be shared with the low power amplifyingunit 120. FIG. 1 shows a case in which the common source node of thethird and fourth MOSFETs N3 and N4 is shared with the low poweramplifying unit 120; however, the present invention is not limitedthereto.

The power amplifying part 112 may include a single cascode amplifier inthe case in which the driving amplifying part 111 receives and amplifiesa single signal, and include at least two cascode amplifiers in the casein which the driving amplifying part 111 receives and amplifies abalanced signal. As shown in FIG. 1, the power amplifying part 112 mayinclude third and fourth cascode amplifiers 112 a and 112 bcascode-connected to each other in parallel in the case in which thebalanced signal is input to the driving amplifying part 111 by way ofexample. However, the present invention is not limited thereto.

The third cascode amplifier 112 a may include fifth and sixth MOSFETs N5and N6 cascode-connected to each other, and the fourth cascode amplifier112 b may include seventh and eighth MOSFETs N7 and N8 cascode-connectedto each other. Gates of the sixth and eighth MOSFETs N6 and N8 may beconnected to each other as a common gate and have a gate signal Vg_PAinput thereto.

A signal amplifying operation of the first and second cascode amplifiers111 a and 111 b of the driving amplifying part 111 and the third andfourth cascode amplifiers 112 a and 112 b of the power amplifying part112 is known in the art. Therefore, a detailed description thereof willbe omitted.

The low power amplifying unit 120 or the high power amplifying unit 110is selectively operated according to a selection of the user. That is,when the user is to amplify the input signal to a high power levelhaving a preset power level range, he/she operates the high poweramplifying unit 110 and does not operate the low power amplifying unit120. On the other hand, when the user is to amplify the input signal toa low power level having a power level range lower than the high powerlevel, he/she operates the low power amplifying unit 120 and does notoperate the high power amplifying unit 110.

The low power amplifying unit 120 may share the common source node ofone of the first and second cascode amplifiers 111 a and 111 b of thedriving amplifying part 111 of the high power amplifying unit 110 tothereby receive the input signal. FIG. 1 shows a case in which the lowpower amplifying unit 120 is connected to the common source node of thesecond cascode amplifier 111 b to thereby receive the input signal;however, the present invention is not limited thereto.

The low power amplifying unit 120 may include an amplifying part 121amplifying the input signal and a switching part 122 opening or closinga signal transfer path according to a selection of the user.

The amplifying part 121 may include at least one amplifier Q amplifyingthe input signal from the shared common source node, and include aninductor L, a resistor R, and first and second capacitors C1 and C2 as aperipheral circuit of the amplifier Q.

The amplifier Q may be formed of an N type MOSFET having a sourceconnected to the shared common source node, a drain connected to theswitching part 122 through the second capacitor C2, and a gate connectedto a ground through the first capacitor C1. In addition, the gate mayinclude a gate signal Vg2 input thereto through the resistor R.

The switching part 122 may include a first switch SW1 connected betweenone end of a secondary winding S of the coupling unit 130 and a ground,and include a capacitor COUT and a second switch SW2 connected to eachother in series between the other end of the secondary winding S and aground.

The first and second switches SW1 and SW2 may switch on or switch offbetween one end of the secondary winding S of the coupling unit 130 andthe ground or between the capacitor COUT connected in series with theother end of the secondary winding S and the ground, according to apower mode selection of the user.

The coupling unit 130 may have a primary winding P and the secondarywinding S. One end and the other end of the primary winding P mayreceive the balanced signal from the high power amplifying unit 110, andthe secondary winding S may convert the balanced signal into a singlesignal by electromagnetic coupling with the primary winding and outputthe converted signal. In addition, the secondary winding S may beconnected to the switching part 122 to thereby output the signalamplified from the low power amplifying unit 120, as described above.

An impedance matching part 140 may match an impedance of a signaltransfer path between the driving amplifying part 111 and the poweramplifying part 112 of the high power amplifying unit 110.

Describing an operation of the power amplifier according to theembodiment of the present invention in detail, when the user selects thehigh power mode, the MOSFETs of the first to fourth cascode amplifiers111 a, 111 b, 112 a, and 112 b are turned on by the gate signals Vg1 andVg_PA, and the input signal is amplified through the driving amplifyingpart 111 and the power amplifying part 112 and is then output throughthe coupling unit 130. At this time, the MOSFET of the amplifying part121 is turned off by the gate signal Vg2, such that an operation of theamplifying part 121 is stopped, and the first and second switches SW1and SW2 are switched on to thereby allow one end of the second winding Sto be connected to the ground and allow the capacitor C connected to theother end of the secondary winding S to be connected to the ground.

On the other hand, when the user selects the low power mode, the MOSFETsof the first to fourth cascode amplifiers 111 a, 111 b, 112 a, and 112 bare turned off by the gate signals Vg1 and Vg_PA, such that an operationof the high power amplifying unit 110 is stopped, the input signal istransferred to the amplifier Q of the amplifying part 121 connected tothe common source node through the third MOSFET N3 of the second cascodeamplifier 112, and the MOSFET of the amplifying part 121 is turned on bythe gate signal Vg2, such that the amplifier Q amplifies the inputsignal. Here, even if the input signal is the balanced signal, only asingle signal component transferred to the third MOSFET N3 of the secondcascode amplifier 112 may be amplified. Meanwhile, the first and secondswitches SW1 and SW2 are switched on, such that the signal amplified bythe amplifying part 121 is transferred to the secondary winding S and isoutput through the other end of the secondary winding S.

When the user selects the low power mode, the operation of the highpower amplifying unit 110 is stopped and the first and second switchesSW1 and SW2 are switched off, such that an impedance at a primary sideviewed from the secondary winding S of the coupling unit 130 has asignificantly large value. Therefore, an impedance viewed from the lowpower amplifying unit 120 may be almost the same as that of an outputterminal.

FIG. 2 is a simulation view of a resistance value viewed from a lowpower amplifying unit of a multi-mode power amplifier according to anembodiment of the present invention.

Referring to FIG. 2, a real-number part of an impedance Z_low viewedfrom the low power amplifying unit 120 becomes smaller as a capacitanceof the capacitor COUT becomes larger, which is not a matching point forallowing an amplifier Q having a small magnitude for low poweramplification to generate a large output. Therefore, it is difficult toimplement output impedance matching. It may be appreciated that when acapacitor COUT having a capacitance of, for example, about 4 pF is used,a real-number value is reduced from 50 ohm to 6.5 ohm. Therefore, thesecond switch SW2 is used to connect or open between the capacitor COUTand the ground, whereby the impedance may be easily matched in the lowpower mode.

In addition, the first and second switches SW1 and SW2 are not connectedin series with the signal transfer path but are connected to the ground,such that it may be less influenced by break-down generated in theswitch formed in the signal transfer path, whereby a reduction in powerefficiency and linearity may be minimized.

FIG. 3 is a graph showing linearity and efficiency of a multi-mode poweramplifier according to an embodiment of the present invention; and FIG.4 is a graph showing a power gain and efficiency of a multi-mode poweramplifier according to an embodiment of the present invention.

Referring to FIG. 3, it may be appreciated that when IMD3 (A) in a lowpower mode is compared with IMD3 (C) in a high power mode, an efficiencypeak is generated once more at a point at which an output is lower than28 dBm, which is the maximum linear output, by 13 dBm. When a referenceof the linearity is set to IMD3-25 dBc, linear power of 16 dBm or moreand efficiency of 30% or more at this time may be obtained (Seereference signs B and D). Therefore, the efficiency increases byapproximately 20% or more as compared to the single mode power amplifieraccording to the related art, whereby a call time of a mobilecommunications terminal may be very effectively improved.

Referring to FIG. 4, power gains G and E and efficiencies H and F in thehigh power and low power modes of the power amplifier according to theembodiment of the present invention may be appreciated.

It may be appreciated that the power gain in the high power mode ishigher than the power gain in the low power mode. On the other hand, itmay be appreciated that the efficiency in the low power mode is higherthan the efficiency in the high power mode in 16 dBm or less in the sameoutput dBm.

As described above, according to the embodiment of the presentinvention, a two-stage amplifier is used at the time of the high powermode, a single amplifier in which the common source node of theamplifiers is shared is used at the time of the low power mode, and thesecondary winding of the coupling transformer is connected to or openedfrom the ground at the time of selection of the high power and low powermodes, such that an additional impedance matching circuit is notrequired, whereby power loss may be reduced while a circuit area andmanufacturing costs are reduced. Therefore, a battery lifespan and acall time of the mobile communications terminal using the multi-modepower amplifier according to the embodiment of the present invention maybe improved, and call quality may be improved. In addition, themulti-mode power amplifier according to the embodiment of the presentinvention may be configured as a single chip using the CMOS process,whereby the mobile communications terminal may be miniaturized.

As set forth above, according to the embodiment of the presentinvention, the common source node of the cascode amplifier is used incommon and the output is selectively connected to the secondary windingof the coupling unit, such that a separate impedance circuit is notrequired at the time of operations in the low power mode and the highpower mode, whereby manufacturing costs and a circuit area may bereduced.

While the present invention has been shown and described in connectionwith the exemplary embodiments, it will be apparent to those skilled inthe art that modifications and variations can be made without departingfrom the spirit and scope of the invention as defined by the appendedclaims.

1. A multi-mode power amplifier comprising: a high power amplifying unitincluding at least one cascode amplifier to amplify an input signal to ahigh power level having a preset power range; a low power amplifyingunit sharing a common source node of the at least one cascade amplifierto amplify the input signal to a low power level having a power rangelower than the high power level; and a coupling unit coupling a transferpath of a signal output from the high power amplifying unit and atransfer path of a signal output from the low power amplifying unit toeach other.
 2. The multi-mode power amplifier of claim 1, wherein thelow power amplifying unit includes: an amplifying part including anamplifier amplifying the input signal from the shared common source nodeto the low power level; and a switching part including at least oneswitch opening or closing the transfer path of the signal through whichthe signal amplified from the amplifying part is transferred to thecoupling unit according to a selection of power modes.
 3. The multi-modepower amplifier of claim 2, wherein the coupling unit includes a primarywinding receiving the signal amplified from the high power amplifyingunit and a secondary winding receiving the signal amplified from the lowpower amplifying unit and electromagnetically coupled to the primarywinding to thereby couple the transfer paths of the signals to eachother.
 4. The multi-mode power amplifier of claim 3, wherein theswitching part includes a first switch connected between one end of thesecondary winding and a ground to thereby transfer the signal amplifiedfrom the amplifying part to the secondary winding or connect one end ofthe secondary winding and the ground to each other.
 5. The multi-modepower amplifier of claim 4, wherein the switching part further includes:a capacitor connected to the other end of the secondary winding fromwhich the signal is output; and a second switch connected between thecapacitor and the ground and being switched on or off together with thefirst switch, thereby connecting or opening between the capacitor andthe ground.
 6. The multi-mode power amplifier of claim 2, wherein theamplifying part is an N type metal oxide semiconductor field effecttransistor (MOSFET) having a drain outputting the amplified signal, asource connected to the common source node, and a gate receiving a gatesignal.
 7. The multi-mode power amplifier of claim 1, wherein the highpower amplifying unit includes: a driving amplifying part includingfirst and second cascode amplifiers connected with each other inparallel to thereby amplify the input signal according to a set gain;and a power amplifying part including third and fourth cascodeamplifiers connected with each other in parallel to thereby amplify thesignal amplified from the driving amplifying part according to a setgain.
 8. The multi-mode power amplifier of claim 7, wherein the lowpower amplifying unit shares a common source node of the first or secondcascode amplifier of the driving amplifying part.
 9. The multi-modepower amplifier of claim 1, wherein the input signal is a single signalor a balanced signal.
 10. The multi-mode power amplifier of claim 7,wherein the high power amplifying unit further includes an impedancematching part matching an impedance of a transfer path of the signalbetween driving amplifying part and the power amplifying part.